Close the loop

Traceability

One dashboard that answers the question every test-engineering review circles around: does the whole chain still agree? Requirement to test, test to board net, net to routed copper, program limit to the limit each lot actually ran — every hop joined deterministically, every disagreement attributed to the pillar that owns it.

Overview

The traceability dashboard is the one surface where all four pillars of a test project meet. It is not a report generator — it recomputes its verdicts from the live artefacts on every load, so it is incapable of showing a stale green.

Traceability dashboard header and closed-loop chain — Fig. 1 — The demonstration project: 4 joins · 4 pass, 34/34 tests traced end to end, one production-marginal test surfaced with its Cpk.

No LLM sits anywhere in this pipeline. Every verdict is reconciled mechanically — same inputs, same answer — so the dashboard and the chat assistant can never disagree with each other.

The joins

Four deterministic joins — reconciled mechanically, so the same inputs always give the same answer. Names are allowed to drift between artefacts; the chain still holds.

Join	What it catches
Spec ↔ Program	Coverage gaps (a requirement no test implements) and limit drift — a program limit looser than the datasheet is a compliance error, attributed to the pillar that owns each number.
Program ↔ Board	A program that drives a pin the board does not route, a board pin no test uses, a power rail mapped to a digital channel.
Schematic ↔ Copper	A net the schematic declares but no routed copper carries — so a requirement that looks covered on paper is exposed as unreachable on the physical board, tester-side series-termination and Kelvin nets included, disclosed as such.
Program ↔ Production	The limits a lot actually ran versus the limits the program has now — historical drift is reported as drift, never mislabelled as a spec violation.

Fig. 2 — A single closed-loop chain row: requirement REQ-011 (SIO output high) followed to its lot statistics.

How it works

Every load reviews the four pillars fresh — the ingested spec, the program workbook (the dashboard labels which copy it reviewed), the saved board design, and the production STDF — and reconciles values by what they mean, so 65 uA and 65e-6 A compare as equal. Attribution is the point: on real customer data the limit sources legitimately differ, and the difference between "the lot ran at a recorded limit" and "the program violates the spec" is the difference between a finding and a false alarm. The joins compose into one row per test — spec → program → nets → copper → lot Cpk, with debug suspects ranked for any marginal test — and a missing pillar renders as awaiting data with the action that unlocks it, never as a silent pass.

Traceability dashboard with the closed-loop chain rows — Fig. 3 — Detail from the same dashboard (Fig. 1): each test's hops render as linked pills; the production hop carries the lot's Cpk and this board's likely debug suspects.

Requirement → copper

The chain does not stop at the netlist. Select a requirement in the PCB Designer and its nets — including the tester-side series-termination and Kelvin force/sense extensions, disclosed as such — light up on the routed board, aligned with the copper by construction, never by luck.

Requirement dropdown with REQ-014 selected and its traces highlighted amber on the routed board — Fig. 4 — The Highlight-requirement dropdown with REQ-014 (Device ID read) selected: the chip below it names the requirement's 11 nets, and their 36 routed traces render as an amber overlay on the demonstration load board.

Proven end to end

The demonstration project closes the loop completely: 34 of 34 tests trace spec → program → copper → production, and all four joins pass. The final-test lot shows test 1100 (active supply current) at Cpk 0.27 — drifting across four lots while wafer sort stays healthy — with the likely board-side suspects (U1, R2, R9) named by the production hop. And the SIO output-level tests, measured at the tester behind a 33 Ω series termination carrying 3 mA — a 99 mV drop the program limits compensate and the test method documents — reconcile as an info-class documented measurement-path compensation, while an undocumented looser-than-spec limit still reports as the error it is.

Honest boundary Offline verdicts are labelled offline. The dashboard's reconciles prove consistency between the artefacts; final compile authority for the program remains the IG-XL toolchain, and the platform never reports offline-green as tool-verified.