Four intelligences, one tool — all wired to the same context.

Type a task in plain English. The context curator scores every file, design, spec, and STDF lot in the project by relevance — transparent scoring you can see and toggle. The pilot reads what an engineer would open, no more, no less.

Output is cited end-to-end. Reuse a prior design? <cite kind="design"/> chip links to /pcb/<id>. Quote a spec? <cite kind="spec"/> deep-links to the requirement. Touch a part? <cite kind="part"/> points at the parts library.

• Reasoning collapsibles — the LLM can emit a fenced reasoning block; the UI renders it as a closed-by-default <details> with "Reasoning · N steps" summary.
• Context curator UI — see every scored item before you send. Toggle items in/out. Hand off the selection to the pilot.
• Workbook + spec aware — the open Excel workbook is ingested as project context; Jama Connect specs + PDF datasheets are section-indexed and citation-ready.
• Reuse-aware delta — when a prior design fits, the pilot reuses it and surfaces the diff. Refdes preserved, parts list cited, additions explicit.
• Live generation pipeline — curate → draft sheets → draft VBA → compile → verify, status visible per stage in the run viewer.

Import the exports your CAD flow already produces — Specctra DSN, IPC-2581, even a PDF schematic — or point a synced repo at doc-ingest and boards import themselves. Each one becomes a typed PCBDesign with canonical circuit-json (the tscircuit shape). Components, nets, copper — all queryable rows the curator scores when the pilot reaches for a reference design.

• Vendor imports with real copper — Specctra DSN in the KiCad, Allegro, and EAGLE dialects brings pads, traces, pours, and drills across; the IPC-2581 path is validated against a real Allegro board export.
• Pilot emits circuit-json directly — no IR conversion. The schematic viewer renders it inline.
• Autorouter round-trip — export Specctra DSN for your router, import the routed .ses session back onto the same design.
• Reference parts library — 35+ devices with pinouts the LLM consults. No hallucinated pin numbers on common parts.
• Reuse with refdes preservation — when a sub-circuit fits, the pilot copies it forward with a delta block (reused / removed / added / renumbered); refdes stays stable so BOM joins keep working.

Drop in a .std or .std.gz lot. The STDF MCP parses V4 records natively (no Python or wasm at runtime) — MIR, PCR, PTR, TSR, HBR/SBR, PRR. Every analytical view the pilot can call sits behind a tool the LLM can reach for in-chat.

• Seven chat tools the LLM calls in-flight — yield_summary, parametric (per-test mean/σ/Cp/Cpk), first_fail_pareto, test_time_pareto (TSR.TEST_TIM × EXEC_CNT primary + datalog-PTR fallback), wafer_map, limit_drift, correlate (cross-lot trend by TEST_NUM).
• Yield-by-site + site→socket overlay — flag the outlier socket without spelunking.
• First-failure pareto — distinct from "top failing tests": it counts which test FIRST killed each die. Top entry is the highest-leverage fix.
• Wafer-map with cluster detection — edge / ring / single-quadrant heuristics; pair with physical intuition (probe alignment, CMP uniformity, thermal coupling).
• Limits-vs-spec drift with relaxCandidate flag on tests ≥ 2σ inside the spec window. Quote the σ-headroom in the recommendation.

IG-XL is its own language with its own conventions. ATE·IQ carries a typed knowledge base built against a real working programme — 287 VBT-API entries, each citing its UltraFLEX documentation page. The pilot doesn't reach for a public-internet LLM's guess at what TheHdw.DCVI.Pins(X).SpikeCheck does; it looks up the entry and the prohibition.

• 287 typed VBT-API entries covering 14 instruments detected on a real digital programme. DCVI, DCVS, PPMU, Digital, UltraSource, UltraCapture, Patterns, Utility, DSSC, DIB, SyncPanel, MWReceiver, MWSource — each carrying identity, electrical envelope, settle times, prohibitions.
• 30+ VBA quality rules (R01–R33 today, and growing) across dev / prod profiles. Catches On-Error patterns, hardcoded GPIB addresses, per-pin loops, ActiveSites enumeration outside report formatting, Hungarian-prefix mismatches, blocking-timing primitives, missing PassFail writes.
• 20+ cross-sheet rules on every generation. Arg-ceiling (Arg60+ unusual), opcode allowlist, Flow → TestInst / Limits / Binning resolution, sheet-ref resolution, timeset-entry resolution, TName/TNum pairing, Pin Levels Tdelay sanity, unused-bin and unused-test-instance detection, tf* procedure-prefix convention.
• Spec ingestion — Jama Connect API sync or drop a PDF datasheet. Section-indexed; citation-ready in chat. <cite kind="spec" id="<specId>#<reqId>"/> deep-links to the cited requirement.
• .igxlproj schema in the system prompt — generator output isn't a guess at the project XML shape. The full 7-block schema with every required sub-field is embedded so IGLinkCL actually compiles the output.
• Generation contract regression test — the reference programme's .igxlProj is the schema oracle. A future prompt edit that drops a mandatory block breaks the test loudly.
• IG-Link CLI integration — compile runs are first-class artefacts. The Run viewer at /runs/[id] shows the diff, the Validation tab, the build log, all downloadable.