Decide which DUT pin lands on which tester channel, site by site, against the real tester configuration — and save it once. The saved plan is the program's channel contract: the generated channel map, the schematic, the board check, the IG-XL agent and the DIB checker all read that one plan, and none of them keeps a copy of its own.
Pins down the rows, sites across, and every choice drawn from the instruments the tester configuration actually contains. Start from the pins you already have — the spec, an imported board, an existing program's pin and channel maps, or a list typed by hand. Paste the tester's configuration and assignment becomes type-aware: a digital pin is offered digital channels, a power pin DCVI channels with force and sense. Auto-assign fills the blanks with channels of the right family and checks its own proposal against the DIB catalogue before offering it; a channel you picked is kept exactly as you left it.
| Surface | Reads the plan for |
|---|---|
| Generated program | Your picks emitted into the IG-XL project's channel map as chosen. |
| Schematic | Each DUT pin drawn with its planned channel. |
| Board ↔ program sync | The bound board checked against the program; any pin they disagree about is a finding. |
| IG-XL agent | Channel-plan and DIB-check questions answered from the same picks. |
| DIB check — 166 rules | Judged against the same plan. |
The plan also learns from the program: after a program is generated, the channels it needed are written back into the plan (blank cells only, never over a pick you made), so from the second run on the plan already holds what the program needs.
The 166-rule DIB checker runs offline, in the editor on the saved plan and in the analysis hub on an ingested Channel Map sheet. Its catalogue spans the channel picture of a DIB: channel and slot checks, DC instruments and sources, digital channels and their capture and source engines, AC capture, serial and RF. Severity is earned, not assigned by taste: only a rule grounded in documented platform constraints may fail a plan; the rest warn or inform, so a finding's weight tells you how sure the checker is. All 166 rules run on every check, and a rule the plan cannot be judged on is reported as not applicable (never counted as a pass) with its reason.
The saved plan is written to travel. Inbound, the board↔program sync checks an imported board's nets against the program's pins. Outbound, ATE·IQ™ writes the plan as a first draft of the DIB in Cadence Allegro's own input grammar (a netlist and a placement seed that puts the DUT at your template's socket centre), with each net's planned tester channel travelling inside the netlist the layout tool imports. Nothing here draws copper; routing stays with the layout engineer, in the tool that owns it.