Verify

Board Intelligence

Every design gets the same battery of deterministic analyzers — power domains, pin match, test impact, a 166-rule DIB check, geometric and electrical DRC, and a join against production STDF history. No LLM in the verdict path: same inputs, same findings, every time.

01

The analysis hub

One page per design collects every check, always current — never a stale report.

Analysis hub for the demonstration load board
Fig. 1 — The demonstration board's analysis hub: power rails, DIB check, pin match, test impact and STDF history on one page.

The hub covers the board end to end: power rails with their sources, loads and bypass capacitors (eight issue families), checked against the tester configuration; the 166-rule native DIB checker, run against the board and the saved channel plan; pin match across board, plan and program, tolerant of naming conventions; and test impact in both directions — which components a test depends on, and which tests a component change would touch. Alongside those sit the applicable subset of 400+ cited ATE load-board rules, production STDF history joined onto the board, and geometric and electrical DRC.

ONE DESIGN the stored design power domains pin match · test impact DIB rules · ATE rules geometric + electrical DRC STDF history join FINDINGS ERROR — cannot pass silently WARNING — review advised INFO — disclosed structure each finding cites its rule id + measured value deterministic checks — no LLM anywhere in the verdict path
Fig. 2 — One design fans out to the analyzers; findings come back classed by severity, each citing its rule and its measured value.
02

The knowledge behind the checks

The rule content is not heuristic. The DIB checker implements a catalogue of 166 rules covering channel assignment, instrument capability and board structure. The ATE design rules are a cited registry of 400+ load-board rules — every rule carries its source, so a finding tells you where the rule came from, not just that a rule fired.

The checkers also know what a DIB is supposed to look like. Series-termination nets and Kelvin force/sense pairs are recognised as deliberate DIB structure and reported as info-class disclosures — not flagged as warnings for the crime of being correct. A checker that cries wolf on every properly terminated net trains engineers to ignore it.

03

Geometric and electrical DRC

On boards with routed copper, the geometric DRC measures the actual geometry: trace width per net class, pad-to-trace clearance, annular ring. Each finding cites its knowledge-base rule id and reports the measured value against the threshold — 0.14 mm measured, 0.20 mm required — so the fix is quantified before anyone opens a layout tool.

A separate class of checks is electrical, and these are errors, not warnings: same-layer crossings between traces of different nets, pad encroachment, and floating vias. A board that is shorted as drawn cannot pass silently. These checks exist because a visually plausible board once carried 78 invisible crossings — plausible is not the standard; measured is.

Routed copper near the DUT after electrical DRC
Fig. 3 — The demonstration board's copper at the DUT after routing against the electrical DRC: 45° bends, zero same-layer crossings, zero floating vias.
04

From yield problem to probe point

The STDF history section joins production lots onto the board, so a test that trends marginal in production turns into a ranked list of components to probe.

The first question at a debug bench is what do I probe? — this section answers it from data already in the project, before the board is on the bench.

05

Proven end to end

On the demonstration board the hub reads coherently: the DIB check passes 102 of 102 applicable rules, pin match reconciles every board pin against the channel plan and the program, and the electrical DRC reports zero errors on the routed copper. With final-test lots joined, the STDF section surfaces test 1100 (active supply current) at Cpk 0.27 and names the debug suspects — U1, R2, R9 — the components in that test's measurement path.

Honest boundary Sections without their input data say so. No saved channel plan means the DIB check reports awaiting-data with the step that unlocks it; no ingested STDF means no history join — never an empty chart dressed as a clean one. And 102/102 means 102 applicable rules: rules whose preconditions this board does not meet are reported as not applicable, not counted as passes.