Board intelligence
Check a load board against the test program before anyone powers it. Open the board and the hub matches its nets to your tester pins, runs a 166-rule DIB check, measures the copper, solves the DC operating point and follows production lots back onto the parts. The same inputs give the same findings, every time.
- Input
- A public Cadence Allegro 17 board, read from its Fabmaster export; a demonstration pin map.
- What ran
- The hub matches its nets to your tester pins and measures the copper.
- What it found
- 15 of 16 tester pins in a demonstration pin map resolve on the board. The one that does not, INDEX, was put into the map on purpose. Copper checks 0 errors, 80 warnings across 12 components.
The analysis hub
One page per board holds every check, computed from the stored design when you open it — never a stale report. A card that lacks its input says which step unlocks it.
| Card | What it answers |
|---|---|
| Pin match | Does every tester pin in the project's pin map land on a board net? |
| DIB check | Does the channel map satisfy the 166-rule DIB checker, and does the board carry the sense nets it declares? |
| Power | Every rail with its source, loads and bypass, checked against the tester configuration. |
| DC operating point | What voltage reaches the DUT, which supplies float, where an effective short sits, whether each pull-up reaches a valid high. |
| Test impact | Which components a test depends on, and which tests a component change would touch. |
| Checks | Copper DRC, electrical errors, connectivity and advisory ATE-shape findings on the board itself. |
| ATE design rules | Built-in load-board design knowledge, each rule carrying a confidence label. |
| STDF history | Production lots joined onto the board, so a marginal test points at parts. |
| ngspice · KiCad DRC | Second opinions from independent tools, on demand where those tools are installed. |
Every verdict is a deterministic check with no language model in the path; each finding names its rule, its severity and (where one applies) its measured value against the threshold.
Solve the board before it is powered
Every board with a netlist gets a DC operating-point solve, computed inside ATE·IQ™ with no SPICE licence, so you know what the DUT will see: the rail voltage at the DUT, supplies left floating, effective shorts, and whether each open-drain pull-up reaches a valid high within the pin's sink current. The solved voltages are drawn back onto the schematic, where the parts are. Where ngspice is installed, the same netlist is solved by a second engine as an independent cross-check.
Checks that know what a DIB is
The rule content is specific to test hardware. A Kelvin sense line is recognised as a measurement trace rather than a supply rail, and a series-terminated signal's tester-side net is followed back to the DUT pin it extends. Neither is flagged for the crime of being correct. A checker that cries wolf on every properly terminated net trains engineers to ignore it. And the STDF history card joins production lots onto the board, so a test that trends marginal in production becomes a ranked list of components to probe, before the board is on the bench.
Measured on a public Cadence Allegro 17 Fabmaster export, checked against a demonstration pin map in which INDEX is a planted miss: pin match 15 / 16; copper checks 0 errors, 80 warnings across 12 components.