PCB layout

Bring in the routed board as your EDA tool wrote it, then work with the copper: zoom through it in 2D, turn it over in 3D, measure it against fab rules, light up the traces behind a requirement, and export a BOM, a KiCad project, Specctra DSN, an IPC-2581 netlist (connectivity only) or circuit-json. Gerbers and the fab package come from the tool that drew the board, since the layout is its own. The copper stays exactly as your EDA tool laid it out; ATE·IQ™ reads and measures it, and never routes it.

A real Cadence Allegro board in the layout tab at 3x: copper pour, traces, plated holes and part designator labels
A public Cadence Allegro 17 board, read from its Fabmaster export, in the layout tab at 3×: the pour, every trace and plated hole, exactly as the export wrote them. No copper is redrawn.
01

Import the board as it was routed

Cadence Allegro Fabmaster, IPC-2581, ODB++, Specctra DSN and KiCad boards import with their copper (pads, holes, vias, traces, pours and the outline) into one stored model in an open format. Imports never write a private format; exports never read one. The full list is on EDA import & export.

02

Inspect it in 2D and 3D

The layout tab zooms through the copper with every part's designator labelled. The 3D tab turns the board over, and downloads it as a glTF binary that opens in any glTF viewer. Pick a requirement and the traces behind its test light up on the board.

The same board in the 3D tab, top view
The same board in the 3D tab. Component bodies are drawn as boxes from their footprints.
03

Measure the copper

The geometric DRC measures the real copper: trace width per net class, pad-to-trace clearance and annular ring, each finding naming its rule and the measured value against the threshold. Electrical faults (a same-layer crossing between nets, a floating via) are errors, not warnings: a board that is shorted as drawn cannot pass silently. Where KiCad is installed, the board can also be run through KiCad's own DRC as a second opinion, on a card of its own.

04

Export

An imported board exports a BOM, a KiCad project, Specctra DSN, an IPC-2581 netlist (connectivity only), circuit-json and, where the import carries a schematic, a page to print or save as PDF. Gerbers and the fab package come from the tool that drew the board, since the layout is its own.

Boundaries Layout authority stays with the tool that drew the board: ATE·IQ imports vendor geometry as exported, never re-routes it and is not an autorouter. DRC thresholds default to generic fab minimums.