AI-assisted development for ATE engineers
The test-engineering loop, closed.
ATE·IQ is a development platform for semiconductor test engineers. It takes the four artefacts every test program lives across — the device spec, the IG-XL test program, the load board, and the production STDF data — and joins them into one traceable, machine-checked loop. AI drafts and explains; deterministic engines verify. Everything runs on the engineer's own machine.
Why it exists
A production test program is never one file. The device limits live in a PDF, the program lives in an Excel workbook, the load board lives at a PCB vendor, and the proof it all worked lives in STDF files nobody opens twice. Every question that matters — does the program match the spec? does the board match the program? which component do I probe when test 1100 fails? — crosses at least two of those silos, and today crosses them by hand.
ATE·IQ keeps all four artefacts in one workspace and joins them mechanically — requirements to tests, tests to board nets, schematic nets to routed copper, program limits to the limits each lot actually ran — same inputs, same answer, every time. AI is used where AI is good: drafting programs, authoring boards, explaining failures — and every AI draft is checked and repaired before an engineer sees it.
Those checks now include the device itself. A generated program is replayed against a model of the DUT — derived automatically from a vendor CMSIS-SVD file or the project's own register map, or your own RTL/SystemC model connected as-is; anything that can answer as the part would can be the judge — so semantic errors that compile perfectly, like the wrong register or a compare the silicon can never satisfy, are caught offline instead of on the test floor. Every surface states who judged: your model, or the derived stand-in. What the model cannot judge, it declines out loud.
The platform is grounded in real tester knowledge: a cited registry of UltraFLEX instrument behaviour — envelopes, settle times, prohibitions — authored in our own words, every claim carrying its source, alongside a working reference programme and 400+ cited ATE load-board design rules. When ATE·IQ makes a claim about an instrument, a settle time or a DIB rule, the claim carries its source.
Feature guide
Each page below explains one capability end to end — what it does, why it can be trusted, and what it looks like on the demonstration project.
Test programs
Spec Ingestion
Datasheet PDF or Jama Connect in; structured requirements with limits, forced conditions and test numbers out.
Read →Test Program Generation
Spec to complete IG-XL project — sheets, VBT modules and digital patterns — checked and repaired before you see it.
Read →Device-Model Verification
The generated program replayed against a model of the device — derived from a vendor SVD file, or your own RTL connected as-is — catching semantic errors that compile cleanly, with DV waveforms and honest declines.
Read →Pattern Generator
Configure SPI or I2C and a transaction sequence; get cyclized IG-XL digital patterns and a live, semantically-labelled waveform.
Read →Excel & Live Workbook
ATE·IQ inside the open IG-XL workbook: live sheets and VBA as context, quality analysis, edits applied in place.
Read →Code Map
Dependency map across VBA, patterns and sheets — active-function coverage, quality scans, and a pattern-to-test graph.
Read →PCB design
Schematic Design
The logical board, authored in ATE·IQ — multi-sheet ATE schematics with DUT-first sheets, drawn terminations and Kelvin legs, channel flags consistent with your channel plan by construction, and checked live edits with history.
Read →PCB Layout
The physical copper, imported verbatim from your CAD flow — IPC-2581, ODB++, Specctra, KiCad, SES — then DRC-checked, bound to the schematic, requirement-traced, and exported to fab.
Read →Board Intelligence
Nine analyzers over every design: power domains, pin match, test impact, geometric and electrical DRC, 166-rule DIB check.
Read →Channel Map Designer
The DIB definition as a first-class artefact — pins to tester channels, checked against the board and the program.
Read →PCB Generator
Describe the load board; ATE·IQ authors it against your spec — checked and repaired before you see it.
Read →Production data & the loop
STDF Analytics
Native STDF V4 parsing — yield, Cpk, outlier screens, drift, wafer maps — and statistics-backed limit proposals fed back to the program.
Read →Traceability
One dashboard for the whole chain: requirement to test to net to copper to lot, every hop reconciled and attributed.
Read →ATE·IQ Chat
A co-pilot that sees your project — curated context, real tester knowledge on tap, and answers that cite their sources.
Read →Context Curator
See and shape exactly what the model receives — scored artefacts, honest budgets, one-click handoff to chat.
Read →Architecture & Security
Local-first by design: everything runs on the engineer's own machine, credentials encrypted at rest, and the only egress is what you point it at — prompts on your own LLM keys.
Read →The demonstration project
Every page in this guide references the same live project: a small SPI temperature sensor taken through the entire loop inside ATE·IQ — spec to program to board to copper to production data.
- Spec in.
The device datasheet becomes 34 structured requirements — DC, SPI protocol, register and temperature-accuracy tests — each with limits, forced conditions and a test number.
- Program generated.
ATE·IQ generates the full IG-XL project: Flow, TestInst, Limits, Binning and Pin Levels sheets, a VBT module implementing all 34 tests, and 24 deterministic SPI pattern files. 100% requirement coverage, all pins attributed.
- Board designed.
A five-sheet UltraFLEX-class DIB schematic — DUT, signal conditioning, power, DCVI and digital I/O — with series terminations, Kelvin force/sense, ESD clamps, and routed copper that passes the electrical DRC clean.
- Production data joined.
Wafer-sort and final-test STDF lots parse natively. One test trends toward marginal (Cpk 0.27) and the dashboard names the board components to probe first.
- Loop closed.
The traceability dashboard shows 34 of 34 tests traced end to end — requirement → test → net → copper → lot — with every reconcile green and one documented measurement-path compensation disclosed, not hidden.
What ATE·IQ does not do
Three deliberate boundaries, because a verification tool that overstates itself is worse than none. First: offline checks are labelled as offline — final compile authority for a generated program remains IG-XL itself, and ATE·IQ says so rather than claiming tool-correctness it cannot prove. Second: statistics-backed limit proposals are proposals; the tool never silently edits a production limit. Third: when data is missing — no channel plan saved, no STDF ingested, no scan run — the surface says awaiting data and shows the step that unlocks it, instead of rendering an empty chart as if it were a clean one.
Talk to us
The useful first conversation is a walkthrough on your device and your tester — a spec you already ship, a workbook you already maintain. Tell us what you are working on and we will reply within one business day.