For IG-XL test engineering teams

From spec to a checked IG-XL program.

Pick a spec and ATE·IQ™ writes the IG-XL program — the sheets, the VBT code and the digital patterns, with every test keyed to its requirement's test number. It checks the code, the tester setup and the limits, replays the tests against a model of the device and lists any it cannot judge, and hands you a checked project ready for IG-XL's offline simulator. Then the integrated IG-XL agent refines it with you, live in the workbook.

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Everything that can be derived is written by code; the language model is used where engineering judgement is needed.
Judged by checkers, a device model and, when you choose, IG-XL's own offline simulator — rather than by the language model that wrote it.
ATE·IQ runs on your machine, and project data goes only where you point it: your LLM provider and any repository, Jama server or model endpoint you connect.

Pick a spec and generate: every requirement stays in view with its test number. Shown on an example project: a six-requirement read-back spec for an open-source I²C core.

The model drafts; the checkers decide.Pre-flight, the device model and IG-XL's own simulator judge the program; every join between spec, program, board and production is a deterministic engine the agent calls and explains.

Demonstration project · a small motion sensor with a 4-wire SPI interface · synthetic data, defects planted on purpose
Test	Result	Measured	Under what conditions
Datalog rows on IG-XL's offline simulator	AS PREDICTED	25 / 25 · Bin 1	a generated 16-test program run by IG-XL itself, on simulated instruments on one site, with the device's serial reads supplied by its model; it is not a tester result
Spec limits against the program	FLAGGED	1 of 16	a spec limit tightened after generation, which the program never picked up; planted on purpose

VBA review: 33 rules, with findings at the exact line, in Excel and on synced programs.

Test programs

Generate → check → verify → run.

One focused pass per requirement: serial and digital tests get a real, deterministic pattern file and the code that runs it, and DC tests get measurement code grounded in built-in IG-XL and UltraFLEX platform knowledge. Then the checkers decide, and the tests are replayed against a model of the device before you open the program.

IG-XL agent

Then refine it with the integrated IG-XL agent.

Load the generated project in IG-XL and carry on with the agent beside it. Open it from the ATE·IQ tab in Excel and it follows every sheet and the cell you are on, streamed every few seconds while connected, and re-reads the VBA editor's current state, unsaved edits included, as you work. Ask it to explain a test or change a limit: it answers with tools that compute rather than recall, stages the change with its before and after, and waits for your Apply.

Follows the program you have open, in Excel or loaded in IG-XL.
Every edit is previewed, applied on your click, and reversible.
VBA it drafts is checked against the IG-XL API before it is offered to you.

The ATE·IQ agent window beside Excel on Example_Program.xlsm: asked to tighten the upper limit of Iq_3V3_Active to 60 µA, it stages a one-cell change on the Flow sheet's Use-Limit row, 7.5E-05 to 6E-05 at Flow!L14, with Dismiss and Apply buttons — The agent's window beside Excel. Asked to tighten a limit, it stages the one-cell change on the Use-Limit row IG-XL reads, notes how close the example's placeholder value sits to the new limit, and waits for your Apply. Captured on an invented example program, not the program generated from the spec above; its remark about real silicon is the model's own reasoning from that placeholder value, not a measurement.

Load boards

Read the board your EDA tool wrote. Check it against the program.

Cadence Allegro netlist and Fabmaster exports import natively, with no Cadence licence; IPC-2581, ODB++, Specctra DSN, KiCad and PDF schematics too. Every pin in the program's pin map is checked against the board's nets, the copper is measured, the 166-rule DIB check runs, and a DC operating-point check reports rail voltages at the DUT before the board is ever powered. Layout stays in your EDA tool; ATE·IQ never draws copper.

A real Cadence Allegro board, read from its Fabmaster export, in the layout tab at 3x zoom — A real Cadence Allegro 17 board, read from its public Fabmaster export, checked against a demonstration pin map that carries one planted miss. Inset: the analysis hub's Pin match card for that check against the demonstration pin map. The miss is `INDEX`: the pin map names it, and the board has no net or pin for it.

The analysis hub's Pin match card: 15/16 tester pins match the PCB, 1 doesn't resolve, likely a pin-map gap; 15 matched, 1 mismatched, 8 warnings — A real Cadence Allegro 17 board, read from its public Fabmaster export, checked against a demonstration pin map that carries one planted miss. Inset: the analysis hub's Pin match card for that check against the demonstration pin map. The miss is `INDEX`: the pin map names it, and the board has no net or pin for it.

Production data

The ground truth, parsed where it lands.

STDF V4 lots parse natively on the engineer's machine — yield by site and bin, Cpk, drift, wafer maps and outlier screens. The traceability dashboard joins every lot back onto the program and the spec and names the limit one of them no longer shares, and lot statistics become limit proposals that are never written for you.

Wafer map of a demonstration wafer: fails concentrated around the rim, and a lower-right cluster marked by the detector — Wafer 1 of the demonstration wafer-sort lot (synthetic data). Fails around the rim are the planted edge signature; the dashed box is a cluster the detector marks, and it also marks clusters on wafers where none was planted.

Security

Everything on your machine.

Specs, programs, boards and production data are stored in a local database, and the app's services listen only on the machine itself. Your project data leaves only where you point it: prompts to your own LLM provider, on your own keys, and any git repository, Jama Connect server or external device-model endpoint you connect.

Security & deploymentRun it on your own workstation and point it at the LLM provider your organisation already contracts.

One workspace

Spec, program, board and production — held together, checked against each other.

A production test program is never one file. The limits live in a spec, the program in an IG-XL workbook, the board in your EDA tool and the proof in STDF files — four artefacts, four owners, and the mistakes that cost a week live in the gaps between them. ATE·IQ keeps all four in one workspace, checks every hop between them, and puts the agent where it can reach all four.

Fig. 1 — The loop. The program is generated from the spec and refined with the agent, where edits happen; every hop between spec, program, board and production is checked, and the agent can reach all of them.

Boundaries

Offline is labelled offline: IG-XL remains the compile authority. A clean pre-flight is not IG-XL's verdict, and a simulator run (simulated instruments, one site) is not a tester result, nor silicon. A simulator run needs an IG-XL installation.
A verdict is only as good as its model: a derived model agrees with the register map and electrical pack as transcribed, and a connected model's verdicts reproduce that model, so a wrong model gives wrong verdicts with full confidence. IG-XL never runs a connected model.
Proposals stay proposals: limit proposals never write a limit, and workbook edits wait for your Apply.
Missing data says so: a surface without its inputs reads awaiting data, not "clean".
The prose is the model's: the tools compute their figures deterministically, but the answer around them, tables included, is written by the language model you configured, so check a figure that matters against the tool.
It does not draw copper: ATE·IQ reads, views and verifies the load board; layout stays with the EDA tool that drew it.

Talk to us

The useful first conversation is a walkthrough on your device and your tester: a spec you already ship, turned into a checked IG-XL program and refined with the integrated agent — or the agent working in a workbook you already maintain. Tell us what you are working on and we will reply within one business day.

Request a walkthrough sales@ateiq.io